| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 168 | Low Power and High Speed Implementation of 1-Bit Hybrid Full Adder using GDI Techniques Authors:MANDAPATI DURGADEVI, CH.SRIGIRI |
0886-0890 |
Download | |
| IJVDCS 169 | Design and Implementation of Pulsed Latch Based Shift Register Using Body Biasing Techniques Authors:BUDDIGA PRIYANKA, CH.SRIGIRI |
0891-0894 |
Download | |
| IJVDCS 170 | Performance analysis of DEM Circuits with DTCMOS Techniques Using PTM45nm Technology Authors:YANDAPALLI VEERABABU, KILARI JYOTHI |
0895-0897 |
Download | |
| IJVDCS 171 | Design and Implementation of High Throughput and Area Efficient Hard Decision Viterbi Decoder in 65nm Technology Authors:S. SARATH CHAND1, KUPPAM N CHANDRASEKHAR, K.BALACHANDRAR |
0898-0902 |
Download | |
| IJVDCS 172 | Removal of Impulse Noise in Images using Adaptive Decision Tree Based Image Denoising Authors:S. VAISHNAVI, G. SRIDEVI |
0903-0910 |
Download | |
| IJVDCS 173 | Detecting and Correcting Multiple Bit Upsets using Erasure Codes for Protecting SRAM Based FPGAs Authors:D. GNANENDRA REDDY, K. PURNACHANDRA RAO, DR.V.THRIMURTHULU3= |
0911-0916 |
Download | |
| IJVDCS 174 | Implementation of D-Latch Based CSLA for Speed Critical Application Authors:BIJJA REKHA, D.SAILAJA |
0917-0920 |
Download | |
| IJVDCS 175 | Implementation of Brent-Kung Adder Using QCA Technology Authors:MALOTHU KIRAN KUMAR, CH.CURY |
0921-0926 |
Download | |
| IJVDCS 176 | Evaluation of Truncated Multiplier for High Speed and Low Power Applications Authors:E.ASHOK, D.SAILAJA |
0927-0930 |
Download | |
| IJVDCS 177 | VLSI Computational Architectures for the Arithmetic Cosine Transform Authors:D. DIVYASRI, N.ASHOK KUMAR, G.CHANDRASHEKAR REDDY |
0931-0936 |
Download | |
